The present invention relates to semiconductor integrated circuit devices employing insulated gate electrostatic induction transistors.
In the development of VLSI (Very Large Scale Integration) devices, insulated gate transistors (MOS transistors) and insulated gate field effect transistors (MOSFET) are typically used. A cross section of an n-channel MOSFET is shown in FIG. 1. The transistor structure includes a p-type substrate 11 having on one of its major surfaces n.sup.+ regions 12 and 13 which form a source region and a drain region, respectively. Between the source and drain regions is located a doped channel region 14, which is usually formed by injection of boron ions. The latter region has a higher impurity concentration than the substrate 11. The other elements of the device include a channel stop region 15, a gate insulating layer 16 made of SiO.sub.2, Si.sub.3 N.sub.4 or SiO.sub.x N.sub.y, a gate electrode 17 made of n.sup.+ polycrystalline silicon, MoSi.sub.2, WSi.sub.2, Mo or W, a field oxide region 18, a PSG layer 19, a metal source electrode 20 and a metal drain electrode 21.
To further improve the performance of the MOSFET and achieve higher packaging density, the effective channel length L.sub.eff of the device must be reduced. The method currently used to reduce the channel length generally depends on the scaling theory described in R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassaous and A. R. Leblanc, "Design of Ion Implanted MOSFET's with Very Small Physical Dimensions", IEEE, J. Solid State Circuits, vol. SC-9, pp. 256-268, 1974. According to this theory, if the channel length L.sub.eff is to be reduced by a factor of 1/K, other parameters of the transistors are correspondingly changed as shown in Table 1.
TABLE 1 ______________________________________ Parameter Scale factor ______________________________________ device dimensions (T.sub.ox, L.sub.eff, W) 1/K channel impurity concentration (N) K breakdown voltage (V) 1/K current capacity (I) 1/K capacitance (C = .epsilon..sub.ox S/T.sub.ox) 1/K propagation delay time (t.sub.p .alpha. C .multidot. V/I) 1/K power consumption (p .alpha. V .multidot. I) 1/K2 speed power product (p .multidot. t.sub.p) 1/K3 power density (VI/S) 1 wiring resistance (R.sub.L = .rho./W.sub.t) K wiring voltage drop ratio (IR.sub.e /V) K wiring time constant (R.sub.e C) 1 wiring current density (I/W.sub.t) K ______________________________________
In table 1, T.sub.ox is the thickness of the gate oxide (gate insulating layer), L.sub.eff is the effective channel length, W is the channel width, .epsilon..sub.ox is the dielectric constant of the gate insulating layer, S=L.sub.eff W, t is the thickness of the gate electrode, and R.sub.e is the thickness of the gate electrode.
As indicated in Table 1, the gate insulating layer thickness T.sub.ox, channel width W, breakdown voltage V and current capacity I are all reduced by factors of 1/K, whereas the channel impurity concentration N is increased by a factor of K. However, in an actual circuit construction, reducing the breakdown voltage V by a factor of 1/K is difficult and it must, as a practical matter, have a value substantially larger than what this criterion would indicate. As a result, the impurity concentration of the channel assumes a value somewhere between K and K.sup.2. This means N rapidly increases as the length of the channel is decreased. If the channel length L.sub.eff is made smaller than about 1 .mu.m, N becomes far greater than 1.times.10.sup.14 cm.sup.-3 and approaches 1.times.10.sup.17 cm.sup.-3. A normally off MOSFET in which no current flows between the source and drain when the gate voltage is zero can be provided that characteristic only by providing the channel region with a neutral region which will not form a depletion layer. Due to this fact, any attempt at reducing the channel length unavoidably requires a corresponding increase in the concentration of impurities in the channel region.
As the impurity concentration of the channel is increased, the mobility of carriers is decreased (due to impurity scattering) and the current density is decreased. This can cause a drop in transconductance. In terms of electron mobility in the case of silicon, a mobility on the order of 1,500 cm.sup.2 /V sec at an impurity concentration of 1.times.10.sup.14 cm.sup.-3 is decreased to about 700 cm.sup.2 /V sec at a concentration of 1.times.10.sup.17 cm.sup.-3. If the channel impurity concentration is further increased, the carrier inversion layer formed beneath the gate insulating layer becomes very shallow and almost all carriers are subjected to scattering at interfaces between SiO.sub.2 and Si or between Si.sub.3 N.sub.4 and Si, causing an additional decrease in the effective mobility of carriers.
Three distribution curves of electron density in the direction of the depth of an inversion layer with 3 volts applied to a gate electrode formed on an oxide (SiO.sub.2) film 200 .ANG. thick on a p-type silicon substrate are shown in FIG. 2 for impurity concentrations of the substrate of 1.times.10.sup.14 cm.sup.-3, 1.times.10.sup.16 cm.sup.-3 and 1.times.10.sup.17 cm.sup.-3. The concentration at the surface is on the order of 2.times.10.sup.19 cm.sup.-3. For N=1.times.10.sup.17 cm.sup.-3, the electrons in the inversion layer are localized at a depth of about 100 .ANG., but when N=1.times.10.sup.14 cm.sup.-3, the electrons are distributed to 1,000 .ANG. or deeper. Since the mean free path of carriers in silicon is between about 50 and 100 .ANG., almost all electrons in motion are subjected to surface scattering at N=1.times.10.sup.17 cm.sup.-3. When N=1.times.10.sup.14 cm.sup.-3, a substantial proportion of the electrons move in the bulk crystal without being subjected to surface scattering and, as a result, their effective mobility is increased.
Three distribution curves of potential in the direction of the depth of an inversion layer under the same conditions as those for FIG. 2 are shown in FIG. 3. As a matter of course, decreasing the impurity concentration of the substrate is accompanied by a deeper potential distribution in the substrate, which is equivalent to saying that the capacitance between the inversion layer and the substrate is reduced.
The dependency on the substrate impurity concentration of the concentration of electrons induced in an inversion layer for T.sub.ox =200 .ANG. is shown in FIG. 4 for three gate voltages V.sub.g of 2, 3 and 5 volts. For the same gate voltage, the surface electron concentration increases as the substrate impurity concentration is decreased.
These results show that for the same gate voltage, more carriers are induced and their effective mobility is increased as the impurity concentration of the substrate is decreased. In other words, more drain current flows, increasing the transconductance of the device. As a further advantage, the input capacitance of the gate is decreased, thus enabling faster operation of the device. However, if the impurity concentration of the substrate is too low, a depletion layer is formed between the source and drain which permits a current to flow at V.sub.GS =O, and hence the desired normally off characteristic cannot be obtained.
An insulated gate electrostatic induction transistor (MOSSIT) that provides a normally off characteristic without losing the advantages of high carrier mobility and small gate capacitance due to a channel region of low-impurity concentration has been proposed in Japanese Patent Application JPA 56-32757 and in an article by J. Nishizawa, T. Ohmi and H. L. Chen, "A Limitation of Channel Length in Dynamic Memories", IEEE Trans. Electron Devices, vol. ED-27, pp. 1640-1649, 1980. A cross section of such a MOSSIT is shown in FIG. 5. This device differs from the conventional MOSFET in three points: the p.sup.- substrate 31, p.sup.- channel region 32, and p.sup.+ region 34 formed beneath the channel region. The impurity concentration of the p.sup.+ region 34 is made low, for instance, not more than about 3-5.times.10.sup.17 cm.sup.-3, so that no tunnel current can flow between the region and the N.sup.+ drain region 13 in the normal operating voltage range. In order to retain a high mobility, the p.sup.- region 32 usually has an impurity concentration of 1.times.10.sup.15 cm.sup.-3 or lower. The substrate has a low impurity concentation in order to decrease the capacitance of the source and drain regions. The gate region 33 is made of a material that provides the highest possible diffusion potential with respect to the n.sup.+ source region, suitable examples of which are p.sup.+ polycrystalline silicon, silicides such as MoSi.sub.2, WSi.sub.2, TiSi.sub.2, and TaSi.sub.2, and high melting point metals such as Mo, W and Pt. Alternatively, the part of the gate that contacts the gate insulating layer 16 may be made of p.sup.+ polycrystalline silicon and the overlying part may be made of a silicide or a metal. This design reduces the resistance of the gate electrode and is more effective for high-speed operation of the device.
The conventional MOSFET very often uses a gate made of n.sup.+ polycrystalline silicon, but this is not used in the MOSSIT of FIG. 5. If the gate 33 in the device of FIG. 5 were made of n.sup.+ polycrystalline silicon, the resulting decrease in the thickness of the gate insulating layer 16 would bring the surface potential of the channel close to the source potential at V.sub.GS =O. The resulting surface conduction would thus make it impossible to provide the desired normally off characteristic.
The MOSSIT of FIG. 5 is provided with a normally off characteristic not by any neutral area in the channel region, but by forming a potential barrier in the channel resulting from the diffusion potentials of the gate 33 and the p.sup.+ region 34 with respect to the n.sup.+ source region 12. Therefore, it is apparent that the MOSSIT of FIG. 5 uses a very different design concept that the conventional MOSFET.
Further, the device of FIG. 5 further includes a p.sup.+ region 35 and an electrode 36 on the other major surface of the substrate. This is for the purpose of keeping the potential of the highly resistive substrate at a constant level. Yet further, the MOSSIT does not use a substrate bias of the type that is frequently employed with a conventional MOSFET. More specifically, the substrate of the n-channel MOSSIT of FIG. 5 is not negatively biased. With a negative bias applied to the substrate, more of the electrons induced in the channel from the inversion layer are localized in the surface. As shown in FIG. 2, the basic philosophy of the MOSSIT is to permit the induced carriers to flow all the way through to the deepest area, and it is for this reason that the substrate is not given a negative bias. To the contrary, the substrate is forwardly biased to the extent permitted by the diffusion potential.
Because of the low impurity concentration of the channel region, the MOSSIT of FIG. 5 has a high carrier mobility, permitting a flow of a large drain current. However, in order to provide a potential barrier of 0.6 volts at a drain voltage of 3 volts when the substrate and gate are biased to the same potential as the source, the relation L.sub.eff /D&gt;1.6 must be satisfied. In other words, the effective channel length L.sub.eff must be at least 1.6 times as large as the depth of the channel region D. Needless to say, with a lower voltage, the critical value of L.sub.eff /D can be reduced to 1.5, but in no case should L.sub.eff /D be lower than 1.3.
In view of the above considerations, one object of the present invention is to provide a MOSSIT that achieves a higher transconductance with a shorter channel and which performs consistently irrespective of variations in the fabrication process.
Another object of the present invention is to provide an integrated circuit using this MOSSIT.